1. Field of the Invention
The present invention relates to a multilayer chip capacitor, in particular, which can maintain Equivalent Series Resistance (ESR) in a suitable level with reduced Equivalent Series Inductance (ESL).
2. Description of the Related Art
Multilayer chip capacitors have widespread use as capacitive parts for Radio Frequency (RF) circuits. Specifically, they can be used availably as decoupling capacitors arranged in a power circuit of a Large Scale Integration (LSI) chip or device. To stabilize the power circuit, it is necessary that the multilayer chip capacitors have a lower ESL. Such demand is increasing further according to high frequency and low voltage trend of electronic devices. The stability of a power circuit depends on not only the ESL of a multilayer chip capacitor but also the ESR. When the ESR is too small, the stability of the power circuit is weakened and thus the voltage fluctuates abruptly in oscillation. Therefore, it is preferable to maintain the ESR in a suitable value.
As an approach proposed to reduce the ESL, U.S. Pat. No. 5,880,925 discloses a lead structure of first and second internal electrodes located in an “interdigitated” arrangement. FIG. 1a is an exploded perspective view illustrating the internal electrode structure of the conventional multilayer chip capacitor, and FIG. 1b is a perspective view illustrating the exterior of the multilayer chip capacitor shown in FIG. 1b. 
Referring to FIG. 1a, internal electrodes 14 are formed on dielectric plates 11a and 11b, respectively. Dielectric layers 11a and 11b are stacked alternately one on another, thereby forming a capacitor body 20. The internal electrodes 14 include first internal electrodes 12 and second internal electrodes 13 of opposite polarities. A single one of the internal electrodes 12 cooperates with a single one of the internal electrodes 13 to constitute one block, and a plurality of such blocks are stacked one atop another. The first and second internal electrodes 12 and 13 are connected to external electrodes 30 (including 31 and 32), in which the first internal electrodes 12 are connected via leads 16 to the external electrodes 31, respectively, and the second internal electrodes 13 are connected via leads 17 to the external electrodes 32, respectively (see FIG. 2b). The leads 16 of the first internal electrodes 12 are located adjacent to and interdigitated with the leads 17 of the second internal electrodes 13. Since the leads adjacent to each other are supplied with voltages of opposite polarities, magnetic fluxes generated by high frequency currents applied from the external electrodes are canceled with each other between the adjacent leads and thus the ESL is reduced.
In addition, each internal electrode 12 or 13 has four leads 16 or 17. Since resistances created in the four leads are connected in parallel, the entire resistance of the capacitor is also lowered significantly. As a result, the ESR of the capacitor becomes too small. Then, it is difficult to satisfy target impedance and makes a power circuit unstable.
To prevent the ESR from becoming too low, U.S. Pat. No. 6,441,459 proposes the use of a single lead in one internal electrode. However, according to this patent document, currents flow in the same direction through some of internal electrodes which are adjacent to each other in a vertical direction (i.e., in a stacking direction). Then, magnetic fluxes are not canceled between the corresponding internal electrodes which are adjacent to each other in the vertical direction. This as a result increases the ESL.